Category:Vector graphics
Category:Adobe Illustrator1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory which can be set in a power down mode.
2. Description of the Background Art
Japanese Patent Laying-Open No. 2000-227642 discloses a conventional semiconductor memory which can be set in a power down mode. FIG. 9 is a circuit diagram showing a portion of the conventional semiconductor memory. A conventional semiconductor memory 30 includes a power supply control circuit 33, a power down control circuit 35, a power down control signal generating circuit 31, a power down signal generating circuit 32, and a control circuit 34. A sense amplifier (not shown) amplifies data read from a memory cell (not shown) of the semiconductor memory 30.
The power down control circuit 35 sets the semiconductor memory 30 in a power down mode, in response to a power down control signal DD0. The power down control signal generating circuit 31 generates the power down control signal DD0 in response to a power down control signal PWD of a low level.
The control circuit 34 generates a signal in response to the power down control signal DD0, to prevent the power supply control circuit 33 from turning on a power supply voltage supply circuit 36. If the power supply voltage supply circuit 36 is turned on, a transistor 37 is turned off, so that an external power supply voltage VDD is not supplied to a control logic circuit 38. The control circuit 34 causes a transistor 39 to be turned on, when the control circuit 34 receives an output signal of the power down signal generating circuit 32, and causes the transistor 39 to be turned off, when the output signal of the power down signal generating circuit 32 is a low level. Thus, if the power down control circuit 35 outputs the power down control signal DD0, the control circuit 34 causes the transistor 39 to be turned off, thereby preventing the transistor 37 from being turned off. As a result, the external power supply voltage VDD is supplied to the control logic circuit 38. The control logic circuit 38 generates a control signal (not shown) in response to the power down control signal DD0.
The power down signal generating circuit 32 generates a power down signal PWD of a high level. The power down signal generating circuit 32 causes the power down signal PWD to be output to the power down control circuit 35 if the semiconductor memory 30 is in a power down mode.
FIG ac619d1d87
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